The present disclosure relates to controlling the operation of modules on a bus in general, and to coherency control, in particular.
In computer architecture, a bus is a subsystem that transfers data between computer components inside a computer or between computers. For example, multiple modules sharing a shared bus may transfer data to a shared memory to be used by one or more CPUs. Such modules may be, for example, external peripherals, such as, for example, a display control, an LCD control and the like.
Such a module, typically issues an interrupt to the CPU after transferring the data in order to notify the CPU about the transfer. In some cases, the interrupt may be issued before the completion of executing the write instruction and thus, before the data is actually written. For example, such a case may occur since the data may be cached in a buffer, or the execution of the instruction may be pended due to a collision. Such cases may cause the CPU to perform instructions on data that has not yet been stored.
The memory buffer may be a FIFO (first in first out) buffer, which may be used for buffering the data received from the plurality of modules that are connected to the same bus. The buffering is for enabling the bus arbiter to control the whole data received from the plurality of modules for avoiding loss of data.
One method known in the art to avoid the problem of notifying the CPU before the data is written in the memory is by performing a read instruction after a write instruction. In such a method, each module may perform a read instruction after the write instruction for reading one or more blocks from the data written by the write instruction; wherein the reading is for verifying that the data has been written. Since a read instruction has a lower priority comparing to a write instruction, the read will always be performed after the completing of the whole write instruction and, thus reading one or more blocks from the data written by the write instruction ensures the completing of the write instruction. This method is termed herein as “read after write”.
Another method known in the art is to monitor the data lines that connect the bus to the memory. Such a method entails the addition of memory lines and may be cumbersome, expensive and inefficient. Such a method may require the monitoring of about one hundred lines per client device, depending on the bus type.